Constant esp_idf_sys::emac_rmii_clock_gpio_t_EMAC_APPL_CLK_OUT_GPIO

pub const emac_rmii_clock_gpio_t_EMAC_APPL_CLK_OUT_GPIO: emac_rmii_clock_gpio_t = 0;

@brief Output RMII Clock from internal APLL Clock available at GPIO0

@note GPIO0 can be set to output a pre-divided PLL clock. Enabling this option will configure GPIO0 to output a 50MHz clock. In fact this clock doesn’t have directly relationship with EMAC peripheral. Sometimes this clock may not work well with your PHY chip.