Struct esp_idf_sys::spi_bus_config_t

#[repr(C)]
pub struct spi_bus_config_t {

    pub __bindgen_anon_1: spi_bus_config_t__bindgen_ty_1,
    pub __bindgen_anon_2: spi_bus_config_t__bindgen_ty_2,
    pub sclk_io_num: c_int,
    pub __bindgen_anon_3: spi_bus_config_t__bindgen_ty_3,
    pub __bindgen_anon_4: spi_bus_config_t__bindgen_ty_4,
    pub data4_io_num: c_int,
    pub data5_io_num: c_int,
    pub data6_io_num: c_int,
    pub data7_io_num: c_int,
    pub max_transfer_sz: c_int,
    pub flags: u32,
    pub isr_cpu_id: esp_intr_cpu_affinity_t,
    pub intr_flags: c_int,
}

@brief This is a configuration structure for a SPI bus.

You can use this structure to specify the GPIO pins of the bus. Normally, the driver will use the GPIO matrix to route the signals. An exception is made when all signals either can be routed through the IO_MUX or are -1. In that case, the IO_MUX is used, allowing for >40MHz speeds.

@note Be advised that the slave driver does not use the quadwp/quadhd lines and fields in spi_bus_config_t refering to these lines will be ignored and can thus safely be left uninitialized.

Fields

__bindgen_anon_1: spi_bus_config_t__bindgen_ty_1

__bindgen_anon_2: spi_bus_config_t__bindgen_ty_2

sclk_io_num: c_int

< GPIO pin for SPI Clock signal, or -1 if not used.

__bindgen_anon_3: spi_bus_config_t__bindgen_ty_3

__bindgen_anon_4: spi_bus_config_t__bindgen_ty_4

data4_io_num: c_int

< GPIO pin for spi data4 signal in octal mode, or -1 if not used.

data5_io_num: c_int

< GPIO pin for spi data5 signal in octal mode, or -1 if not used.

data6_io_num: c_int

< GPIO pin for spi data6 signal in octal mode, or -1 if not used.

data7_io_num: c_int

< GPIO pin for spi data7 signal in octal mode, or -1 if not used.

max_transfer_sz: c_int

< Maximum transfer size, in bytes. Defaults to 4092 if 0 when DMA enabled, or to SOC_SPI_MAXIMUM_BUFFER_SIZE if DMA is disabled.

flags: u32

< Abilities of bus to be checked by the driver. Or-ed value of SPICOMMON_BUSFLAG_* flags.

isr_cpu_id: esp_intr_cpu_affinity_t

< Select cpu core to register SPI ISR.

intr_flags: c_int

< Interrupt flag for the bus to set the priority, and IRAM attribute, see esp_intr_alloc.h. Note that the EDGE, INTRDISABLED attribute are ignored by the driver. Note that if ESP_INTR_FLAG_IRAM is set, ALL the callbacks of the driver, and their callee functions, should be put in the IRAM.

Trait Implementations

impl Clone for spi_bus_config_t

fn clone(&self) -> spi_bus_config_t

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Default for spi_bus_config_t

fn default() -> Self

Returns the “default value” for a type.

impl Copy for spi_bus_config_t