Constant esp_idf_sys::soc_periph_dac_digi_clk_src_t_DAC_DIGI_CLK_SRC_DEFAULT

source ยท 
pub const soc_periph_dac_digi_clk_src_t_DAC_DIGI_CLK_SRC_DEFAULT: soc_periph_dac_digi_clk_src_t = 5;
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< Select PLL_D2 as the default source clock